1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the device, in particular, a semiconductor device having an anti-fuse element and a manufacturing method of the device.
2. Description of Related Art
Anti-fuse elements that operate on a principle of gate dielectric film breakdown are known as an element for writing data. Such anti-fuse elements operate when a voltage is applied to a gate electrode, which causes a gate dielectric film to break down so that conduction between the gate electrode and the source/drain can occur, thereby performing writing of data.
U.S. Pat. No. 7,277,347 discloses an NMOS structure formed in an N well as an anti-fuse.
Japanese Patent Laid-Open No. 2008-98466 describes a method of simultaneously forming N− diffusion layer regions, which will be source/drain regions of a trench type transistor, and an N− diffusion layer region, which will be a channel region, immediately below the gate of an anti-fuse. According to this document, formation of the N− diffusion layer region immediately below the gate of an anti-fuse stabilizes electric coupling between the gate electrode and the source/drain diffusion layers even when writing data at a low writing voltage.
Japanese Patent Laid-Open No. 2004-111957 describes nitrogen implantation in the channel region of an anti-fuse. According to this document, this allows for a low writing voltage anti-fuse. Japanese Patent Laid-Open No. Hei 9(1997)-045906 discloses a MOS semiconductor device having a pocket structure.